1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a Metal Oxide Semiconductor (MOS) Field Effect Transistor having a trench isolation region and a method of fabricating the same.
2. Description of the Related Art
When fabricating electric power devices such as Liquid Crystal Display (LCD) Driver ICs (“referred to as LDIs”) in semiconductor integrated circuit devices, a low voltage transistor for logic operated at a low voltage and an LCD driving transistor operated at a high voltage should both be embodied together on the same semiconductor substrate. Generally, a high voltage transistor has a structure such as a Modified Lightly Doped Drain (MLDD) and a Field Lightly Doped Drain (FLDD), which includes a thick gate oxide layer. As the increased density of a emiconductor integrated circuit reduces linewidth, trench isolation techniques are thus generally applied to a device isolation region when forming the above electric power devices. For example, in a Shallow Trench Isolation (STI) structure formed using a trench technique, a layer used for gap fill is not a thermal oxide layer but an undoped silicate glass (USG) layer or a Chemical Vapor Deposition (CVD) oxide layer such as a High Density Plasma (HDP)-CVD oxide layer. In addition, in the above described trench isolation process, a nitride liner is typically used.
FIG. 1 is a sectional view of a conventional high voltage MOS Field Effect Transistor having a trench isolation region.
Referring to FIG. 1, a P-type well 101 doped with a P-type impurity or an N-type well doped with an N-type impurity ion is formed on an upper surface of a semiconductor substrate 100. A trench isolation region 107 with an STI structure filled with an insulating material is then formed in a predetermined portion of the well 101. An active region 102 is defined by the trench isolation region 107. A source region and a drain region (not shown) spaced apart from each other by a prescribed distance are formed within the active region 102. Additionally, a channel region is disposed between the source and the drain regions. A gate electrode 106 is formed on the channel region by interposing a gate insulating layer 105.
The gate insulating layer 105 is mainly composed of thermal oxide, in which a thinning phenomenon of an oxide layer disposed on an upper edge of the trench-etched STI structure occurs. In particular, the above-mentioned thinning phenomenon occurs due to the following: a compressive stress induced on a silicon substrate caused by (i) oxidation of the surface of the silicon substrate and a sidewall of the STI structure, (ii) a stress upon a gap fill layer with the STI structure, and (iii) an interruption of the migration of a oxidation reaction gas by a nitride liner formed within the STI structure when thermal oxidation is performed to form a gate oxide layer in the STI structure.
Moreover, the above-mentioned thinning phenomenon leads to what is known as an edge crowding which in turn results in an STI structure being formed structurally with a dent around a boundary between the device isolation region (or a field region) and an adjacent active region. Furthermore, as a result of the oxide layer being thinned due the above mentioned dent, the nitride liner disposed within the STI isolation region becomes a site for trapping charges to an upper portion of the nitride liner, thereby turning on the transistor via the oxide layer. In addition, the above-mentioned thinning phenomenon and dent results in the threshold voltage of the transistor being lowered by the leakage current on the boundary portion of the trench isolation region and the active region to cause malfunctioning of the semiconductor transistor.
Thus, there is a need for a MOS Field Effect Transistor having a trench isolation region which prevents the occurrence of a leakage current on a boundary of the trench isolation region and an active region,